1. Field of the Invention
The present invention relates to a read-only-memory (ROM) and, more particularly, to a ROM which has a memory cell that stores a plurality of bits of information.
2. Description of the Related Art
A read-only-memory (ROM) is a non-volatile memory that is only programmed once. As a result, ROMs are commonly used in applications where the information stored in the ROM is not expected to change.
FIG. 1 shows a block diagram that illustrates a prior art ROM 1. As shown in FIG. 1, ROM 1 includes a storage section 10 that has a plurality of memory cells 12 arranged in rows and columns, and a decoder section 14 that decodes an input address to identify the memory cells 12 in storage section 10 that are to be read. As is well known, each memory cell 12 in storage section 10 permanently stores one bit of information as one of two logic states.
As further shown in FIG. 1, ROM 1 additionally includes a precharge section 18 that, along with decoder section 14, supplies operational voltages to the cells in storage section 10 that are to be read, and a sense amp section 20 that senses the output voltage associated with each of the memory cells 12 that have been read.
In addition, ROM 1 also includes a multiplexor section 22 that passes the output voltages from the memory cells 12 to the sense amp section 20, and a control section 24 that controls the operation of the various sections of ROM 1.
FIG. 2 shows a schematic diagram that illustrates storage section 10. As shown in FIG. 2, each memory cell 12 of the plurality of memory cells formed in storage section 10 is implemented with a single MOS transistor.
In addition, storage section 10 also includes a plurality of word lines WL1-WLn which are arranged so that each word line WL corresponds with one row of cells, and a plurality of bit lines BL1-BLm which are arranged so that each bit line BL corresponds with one column of cells.
Each cell 12 is programmed to store one of the two logic states during the fabrication of the cell by connecting the gate of the transistor to either the source of the transistor if the cell is to store a first logic state, such as a logic "1", or the word line WL that corresponds with the cell if the cell is to store a second logic state, such as a logic "0".
In operation, when a predefined number of memory cells 12 in a row of cells are to be read, such as a byte of cells, decoder section 14 applies a gate voltage to the word line WL that corresponds with the row that contains the cells which are to be read, while grounding the other word lines WL. At the same time, precharge section 18 applies a precharged drain voltage to the bit lines BL that correspond with the cells that are to be read.
If the gate of a particular cell 12 is connected to the source of the transistor, such as the first cell in the first row of FIG. 2, then the gate voltage will not turn on the transistor. This, in turn, allows the bit line BL that corresponds with the cell to remain charged to the precharged drain voltage. As a result, sense amp section 20 senses a "high" voltage condition on the bit line BL, and outputs a logic "1".
On the other hand, if the gate of a particular cell 12 is connected to the word line WL, such as the second cell in the first row of FIG. 2, then the gate voltage will turn on the transistor, thereby causing the bit line BL that corresponds with the cell to be discharged to ground. As a result, sense amp section 20 senses a low voltage condition on the bit line BL, and outputs a logic "0".
Although ROMs are well known, as the systems that utilize ROMs get smaller, faster, and cheaper, the centrality that ROMs play in many applications means that there is a continuing need for ROMs that are faster, consume less power, and require less silicon real estate to implement.